The European Processor Initiative (EIP), an EU-backed pan-European initiative to develop proprietary European processors, has completed its first phase. This phase includes the development of the Arm-based Rhea processor, security technology for HPC and edge processors and a proof-of-concept for the European Processor Accelerator (EPAC) test chip.
For some time now, Europe has wanted to develop its own processor and associated industry, so that the region is less dependent on processors from other regions of the world. To this end, 28 European companies and organizations from ten countries have set up the European Processor Initiative (EIP) consortium. This consortium is also supported by the European Union (EU).
The consortium recently announced that it had completed its first development phase. Based on a budget of 79 million euros, various European companies and start-ups worked on the development of their own processor technology.
Results first development phase
Key achievements from this phase include the introduction of SiPearl’s Arm Neoverse V1-based Rhea processor in partnership with Atos. Although Arm’s technology comes from the United Kingdom, this processor also features 29 open-source RISC-V cores acting as controllers. The use of open source technology is an important part of the pan-European processor initiative. In 2023, this ‘European’ processor should be rolled out in supercomputing environments.
Another result of the EIP project is the development of security technology for HPC and edge computers. So-called ‘crypto tiles’ have now been developed for this purpose. This technology must integrate with other open source processor solutions and applications.
Other solutions
Furthermore, the European Processor Accelerator (EPAC) test chip proof of concept has been developed in the first phase of the EIP initiative. The Barcelona Supercomputing Center and the University of Zagreb (Croatia) have developed so-called vector processing units for high-performance computing power and low energy consumption. This solution is based on the Avispado RISC-V core from Semidynamics from Barcelona.
This project also provided a proof of concept for a built-in compute platform, in combination with an SDK, for the automotive industry.
Phase 2 to start in 2022
The second phase of the EIP is due to start in 2022. In this phase, the consortium wants to focus specifically on bringing the processors developed in phase 1 into production.
