Partners IBM and Samsung Electronics announce the development of a new chip design. By arranging the transistors of a chip in an alternative way, the organizations say they have a method to produce smartphones with week-long battery lives.
Most organizations with an interest in chip development invest in downsizing transistors. The smaller the transistors, the more transistors a chip allows. The more transistors a chip allows, the more effective the chip.
IBM is no exception to the rule. Earlier this year, the organization said it had taken an important step towards the coveted 2 nanometer (nm) transistor. In the same period, Dutch chip manufacturer ASML announced a similar development.
Technology for the production of 2nm transistors creates an important precondition for chip improvement. But there are several roads that lead to Rome. IBM and Samsung Electronics say they have found one of those avenues. Their path does not revolve around the size of transistors, but the spatial arrangement of transistors.
Currently, chip manufacturers such as TSMC and Samsung Electronics use a so-called FinFET design, short for ‘fin field-effect transistor’. IBM and Samsung Electronics are coming out with a VTFET design, short for ‘vertical transport field effect transistors’.
Samsung and IBM say the VTFET design can deliver twice the power and 85 percent less power consumption than FinFET designs. The reason? “A vertical arrangement of transistors, unlike FinFET,” the organizations said.
The image below outlines the design difference. Although IBM successfully tested the design with the production of test chips, the organizations do not specify whether and when the chips will appear on the market. However, the organizations say that VTFET is paving the way for smartphones with more than a week battery life and more effective IoT applications in spaceships and self-driving vehicles.